In integrated circuit memories, there are various ways of controlling the flow of data into and out of the memory. For example, a static random access memory (SRAM) may be operated asynchronously or synchronously. In an asynchronous SRAM, timing for controlling the RAM is accomplished using external logic.
A synchronous (SRAM) is a type of memory that has latches for all inputs and outputs, good drive capability, and a self timed write cycle, all on a single monolithic integrated circuit. A synchronous SRAM is typically used as a high speed cache in a data processing system. When being used as a cache, the synchronous SRAM is under the control of a single system clock. The synchronous SRAM can also be pipelined.
The synchronous SRAM has several advantages over an asynchronous SRAM. First, the synchronous SRAM generally requires fewer external logic chips. Second, the synchronous SRAM can operate at higher system speeds than a comparable asynchronous memory. However, as the synchronous SRAM is required to operate at higher system clock frequencies, timing specifications become increasingly more difficult to meet. For example, it becomes more difficult to test and debug the high speed synchronous SRAM using existing testing equipment. Also, the synchronous SRAM has a relatively small range of clock frequencies at which it can be operated, which prevents the speed of the memory from being reduced for testing and debugging purposes. In addition, manufacturing yields are reduced, and costs increased, because process, power supply, and temperture variations have more effect on the narrow margins that result from reduced cycle times.